module master_interface (

    input wire clk,
    input wire rst,

    //input signals
    input  wire [31:0]  i_master_data,
    input  wire         i_master_en,
    output wire         o_master_busy,

    // signals to slave
    output wire [31:0] o_master_data,
    output wire        o_master_valid,
    input  wire        i_master_ready
    );

    parameter STATE_IDLE = 1'b0, STATE_BUSY = 1'b1;
    reg current_state, next_state;

    // generate next state
    wire handshake = o_master_valid & i_master_ready;
    always @(*) begin
        case (current_state)
            STATE_IDLE: begin next_state = i_master_en ? STATE_BUSY : STATE_IDLE ; end
            STATE_BUSY: begin next_state = handshake   ? STATE_IDLE : STATE_BUSY ; end
        endcase
    end

    // state transition
    always @(posedge clk) begin
        if(rst) begin
            current_state <= STATE_IDLE;
        end
        else begin
            current_state <= next_state;
        end       
    end

    // generate output signals
    reg [31:0] data_reg;
    always @(posedge clk) begin
        if(rst) begin
            data_reg <= 32'd0;
        end
        else if(i_master_en && ~o_master_busy) begin
            data_reg <= i_master_data;
        end
    end
    assign o_master_valid = (current_state == STATE_BUSY);
    assign o_master_data  = ({32{o_master_valid}} & data_reg);
    assign o_master_busy  = (current_state == STATE_BUSY);


endmodule




